Pancha Y. Hertz a, Folla K. Jerome a, Noumbissi S.L. Vanessa a, Wembe T. Evariste b, Essimbi Z. Bernard a, Mohammad Arif Sobhan Bhuiyan c, Khairun Nisa' Minhad c
a Laboratory of Energy, Electrical and Electronics Systems, Department of Physics, University of Yaoundé I, PO Box 812, Yaoundé, Cameroon
b Laboratory of Electronics, Department of Physics, University of Douala, PO Box 2701, Douala, Cameroon
c School of Electrical Engineering and Artificial Intelligence, Xiamen University Malaysia, 43900 Sepang, Selangor, Malaysia
## Abstract
In this study, a time-variant baseline restorer (TV-BLR) circuit was designed and implemented to address the poor frequency selectivity issue in the shaping units of most state-of-the-art readout electronics for CdZnTe/CdTe detectors used in biomedical imaging applications. The proposed circuit improves image quality by canceling the artifacts that result from poor temporal and energy resolution in PET imaging. The proposed circuit consists of a Charge Sensitive Preamplifier (CSP) followed by a classical pole-zero compensation circuit. Two stages of integrators are added and a frequency rectifier module named the TV-BLR circuit has been built. The open-loop amplifier for the CSP is a single-ended input stage amplifier, designed for low-power applications with a maximum power consumption of 43 µW from a 1.2 V supply voltage, verified through post-layout Monte Carlo simulations. The TV-BLR increases the selectivity of the shaping filter, lowers the equivalent noise charge (ENC), and restores the baseline of the circuit to only 143 µV dc-offset. It also extends the counting rate behavior of the system by handling the time-over-threshold (ToT), which depends on the tail current (Itail) of the comparator stage. The circuit was designed, simulated, and validated for an input dynamic of 2–12.5fC, providing an energy range of 55.1–354.3 keV. The design has a charge-to-voltage conversion factor of 56.7 mV/fC with a 4% non-linearity error for an input detector capacitance of 200 fF, while achieving an optimal ENC of 57.4 e − RMS ± 0.1 e−/fC with 13.27 ns peaking time. Process Voltage Temperature (PVT) analysis was performed to validate the simulation results and performance metrics of the design. The proposed design improves energy resolution and avoids energy losses due to the readout system.
## 1. Introduction
Positron Emission Tomography (PET) is one of the most popular medical imaging techniques used for small tumor detection. It is used to create a three-dimensional image by detecting both emitted symmetrical γ-rays created by the annihilation of β + particle of a radiotracer with the electron of the medium [1], [2]. Detection of emitted particle energy is the main work of interest. It can be performed by adding a detector through the direction of emitted particles. Generally, scintillator crystals coupled with a photomultiplier tube (PMT) uses in PET and Single Photon Emitted Computed Tomography (SPECT) emit visible light when radiation interacts with crystal. The mechanical constraints of PMT and the shielding from magnetic fields when combining magnetic resonant imaging (MRI) and PET or SPECT [3] give us to think about another device. Pixel arrays demonstrate the ability to handle the requirement of space efficiency in advanced biomedical imaging like PET, magnetic resonant imaging (MRI) and SPECT [4], [5], [6], [7], [8]. Furthermore, semiconductor detectors such as CdZnTe are highly used for particle physics experiments and also for X-ray imaging using a large matrix of detectors [9], thanks to their good energy and, spatial resolution. It can be also used for PET/SPECT imaging by means of a large matrix of pixels to increase the spatial resolution of the image at the expense of some readout electronics design constraints. The performances associated with the front-end electronics are highly challenging for accurate measurement of soft γ and X-rays in PET/MRI and SPECT applications.
For this purpose, an application-specific integrated circuit (ASIC) that can be integrated into the micrometer dimension allows their placement close to the detector and allows an efficient and low-cost readout acquisition of a multi-channel solution [10]. The key design of such ASIC dedicated to particle tracking detectors involved low power [10], [11], low energy spectrum resolution, low noise and a small area for low-cost requirements. Fig. 1 shows an illustration of the PET imaging readout scheme performed with a pixel detector. ASIC is a good option to achieve small pads and high channel order for high spatial resolution [12] before numerical acquisition based on Field Programmable Gate Array (FPGA). Accordingly, the configuration of the ASIC must be accurately chosen to guarantee low noise, low power, and less chip area. Since Complementary Metal-Oxide Semiconductor (CMOS) technology is the key to ASIC design, the choice of technology scale must be matched to the desired performance. Recently published articles proposed by Manghisoni et al 2010 & 2014 [13], [14] and N. Demaria 2021 [15] have demonstrated the compactness and robustness of the 65 nm CMOS technology for application to ionizing radiation energy readout circuitry. Since, that technology node assures attractive energy efficiency, higher scale integration, low power, and very less chip area applications [12]. Table 1 briefly highlights the design requirements for a single-channel ASIC that must be achieved in this work.
CdZnTe Association (CdZnTe.com)
https://www.cdznte.com/thesis/cmos-readout-fee-based-tv-blr-module-for-cdznte-pixel-detectors-in-high-count-rate-applications.html