## Purpose of guard rings and edge leakage mechanisms
Guard rings (GRs) are electrode structures placed around the active pixel or coplanar-grid region to control electric fields at detector edges and intercept leakage currents originating from surface states, damaged edge regions, and peripheral contact interfaces. Edge leakage arises from increased surface conductivity (due to polishing damage, contaminants, or poor passivation), high-field enhancement at electrode terminations, and imperfect crystal edges. A well-designed guard-ring system reduces lateral field penetration into the damaged surface, collects surface leakage before it reaches the active readout electrodes, and stabilizes the surface potential to preserve charge collection and energy resolution.
## Key design objectives and figure-of-merits
- Minimize leakage current flowing into active electrodes (measured as reduction of dark current and parallel-noise contribution).
- Control electric-field uniformity near edges to avoid local breakdown and charge trapping.
- Maintain active-area fill-factor and spatial resolution (avoid excessive dead area).
- Preserve stable biasing and reproducible surface potentials across temperature and humidity ranges.
- Compatibility with fabrication, packaging, and interconnect constraints in arrays.
Quantitative metrics: leakage current per unit edge length, increase in ENC or FWHM attributable to edge leakage, breakdown voltage margin, and surface-potential uniformity.
## Guard ring geometries and placements
- Single peripheral guard ring:
- A continuous ring surrounding the active array, biased between cathode and anode potentials (commonly grounded or set to intermediate potential).
- Simple and effective for small detectors; reduces direct surface conduction paths.
- Multiple concentric guard rings:
- Two or more rings stepping from the active potential to the detector edge (stepped potentials) create a controlled lateral voltage gradient, reducing high-field regions and spreading leakage current over multiple interceptors.
- Useful for larger dies or where edge damage is extensive.
- Floating guard rings:
- Not externally biased; they assume an equilibrium potential via leakage currents and capacitive coupling. Floating rings can reduce field crowding but may be less controllable than biased rings.
- Pixel-level guard fences:
- Narrow guard traces between pixel edges (guard fingers) in arrays to limit inter-pixel surface leakage and crosstalk; crucial in dense pixel or coplanar-grid arrays.
- Extended guard or collar structures:
- Metal extensions on the cathode or anode surfaces that wrap around edges (collars) to shield active regions from edge fields; useful for planar single-element detectors.
## Biasing strategies
- Grounded guard ring:
- Connect GR to system ground (often same potential as detector cathode or a reference). Simpler wiring, good for intercepting leakage to a defined node.
- Biased guard ring (intermediate potential):
- Apply a potential between cathode and anode potentials to produce a smooth lateral field gradient; reduces local field peaks at electrode terminations. Typical practice: set the GR to a potential slightly above ground (or slightly below cathode) to steer leakage away from active electrodes.
- Resistive divider chain for multiple rings:
- Use a resistor chain to create graded potentials across concentric rings, ensuring predictable voltage steps and avoiding abrupt field changes.
- Floating plus bias combination:
- Outer rings biased, inner rings floating can give both controlled grading and self-adjusting local equilibration.
Choice depends on leakage magnitude, required control, and available contacts/pins.
## Surface passivation and edge conditioning
- Passivation layers:
- Apply dielectric passivation (e.g., SiO2, Si3N4, or polymeric coatings optimized for CZT) to reduce surface states and stabilize surface conductivity. Thicker or lower-permittivity layers reduce capacitance but must avoid introducing contaminants.
- Surface treatments:
- Chemical etching and polishing protocols remove mechanical damage and reduce trap density; bromine-methanol, etch–rinses, or other lab-specific chemistries are used with strict process control.
- Thermal anneals or surface reflow (where compatible) can reduce defect densities.
- Edge trimming and beveling:
- Chamfered or beveled edges reduce field enhancement at sharp corners, lowering breakdown probability and surface leakage concentration.
- Mechanical dicing optimized to minimize micro-cracks reduces leakage sources.
- Guard ring integrate with passivation:
- Pattern passivation to expose GR metal where needed while covering surface between GR and active electrodes to suppress surface conduction.
## Electric field optimization and modeling
- Finite-element electrostatic modeling:
- Use FEM tools to compute 2D/3D electric-field maps for candidate GR geometries, electrode terminations, and passivation stacks. Evaluate maximum fields, field lines penetrating edge damaged region, and weighting-potential distortions.
- Potential grading analysis:
- Model stepped potentials for concentric rings or resistive biasing to ensure smooth lateral field and avoid local high-field spots near ring terminations.
- Breakdown margin assessment:
- Simulate worst-case bias and transient conditions; ensure field at passivation edges and corners remains below breakdown thresholds for CZT and dielectric layers.
- Coupling to charge-transport models:
- Propagate charge clouds near edges to verify that induced signals on active electrodes remain undistorted and that GR collects surface-generated carriers before they reach readout electrodes.
## Layout and dimensioning rules of thumb
- Ring width and spacing:
- Keep guard-ring widths sufficient to provide low impedance collection (typically tens to hundreds of micrometers depending on fabrication) but minimize dead area. Spacing between active edge and first GR should be comparable to or larger than anticipated surface damage zone; typical distances range from tens to a few hundred micrometers in precision devices.
- Number of rings:
- Use additional rings for larger dies or when measured leakage is high; 2–4 concentric rings with graded bias are common in high-performance arrays.
- Edge distance:
- Maintain sufficient clearance between the outermost guard ring and the physical cut edge (avoid placing active structures right at the diced face); include dielectric or epoxy encapsulation near the edge where appropriate.
- Interconnect routing:
- Route guard-ring bias/control traces to a low-noise, low-impedance node; avoid crossing sensitive signal traces to prevent capacitive coupling. Provide discrete resistor networks externally if space or bonding pads are limited.
## Electrical interfacing and readout considerations
- Low-noise biasing:
- Bias networks feeding GRs should be low-noise and filtered; poor filtering can inject noise into the detector. Use RC filtering with high-value resistors to limit current but preserve DC bias and stability.
- Leakage current measurement and monitoring:
- Design for the ability to monitor GR currents (separate sense resistor or instrumented bias supply) to diagnose surface behavior and predict parallel-noise contributions.
- Ground reference and shielding:
- Ensure GR reference shares low-impedance return with system ground/cathode, and shield GR traces to minimize capacitive pickup and crosstalk into readout channels.
## Fabrication and process control
- Metallization choice:
- Select GR metallization compatible with CZT contact chemistry and passivation; ensure adhesion, thermal compatibility, and low contact resistance.
- Lithographic precision:
- Control electrode edges and spacing using reliable lithography; variations in finger edges or ring gaps can create local field enhancers.
- Cleanroom handling:
- Maintain contamination control to avoid conductive residues on surfaces that increase leakage; baking and solvent rinses may be needed post-fabrication.
## Testing, characterization, and iterative optimization
- I–V mapping:
- Measure current vs. bias for active electrodes and GRs separately to quantify leakage collection effectiveness and identify localized high-leakage regions.
- Surface leakage localization:
- Use scanning probe techniques (e.g., micro-IV scans) or IR/optical inspection to locate defects and correlate with leakage hotspots.
- Pulse-shape and spectroscopy tests near edges:
- Compare energy resolution and pulse shapes for events near edge pixels before and after GR implementation to confirm improvement in SNR and reduction of edge-related trapping signatures.
- Environmental testing:
- Evaluate GR performance across temperature and humidity ranges to ensure passivation and biasing remain effective.
- Iteration:
- Modify GR bias, number, spacing, or passivation based on measured leakage and simulation feedback until the design meets leakage and resolution targets.
## Trade-offs and system-level implications
- Dead area vs. leakage control:
- Aggressive GR spacing and multiple rings reduce leakage but increase inactive perimeter, reducing fill-factor—important for tiled arrays where active area efficiency matters.
- Added capacitance:
- Large GRs or close routing can increase capacitance to active electrodes and slightly raise series noise; layout must balance leakage reduction against noise penalty.
- Complexity and cost:
- More rings, resistor chains, and feed lines increase fabrication complexity and assembly cost; choose the minimal effective complexity for required performance.
## Example best-practice checklist
- Perform edge-beveling and optimized dicing to minimize mechanical damage.
- Apply controlled surface etch and high-quality passivation before GR metallization.
- Implement at least one biased GR; use 2–3 concentric rings for larger dies or high-leakage crystals with graded bias via resistor chain.
- Model fields with FEM including passivation to set ring widths and spacings.
- Provide low-noise, filtered bias for GR(s) and ability to monitor GR leakage currents.
- Validate with I–V, transient-current, and spectroscopic tests; iterate geometry and biasing until edge leakage contribution to ENC is negligible.
## Summary
Optimizing guard-ring design for CZT planar detector arrays requires coordinated electrostatic modeling, careful surface processing, considered geometry/biasing choices (single vs. multiple rings, grounded vs. graded potentials), and rigorous measurement-driven iteration. Effective GRs intercept and divert surface leakage, smooth lateral fields to avoid breakdown and trapping, and—when combined with passivation and edge conditioning—significantly improve dark current, energy resolution, and detector stability while balancing fill-factor and added capacitance impacts.
CdZnTe Association (CdZnTe.com)
https://www.cdznte.com/blog/how-is-guard-ring-design-optimized-to-reduce-edge-leakage-in-a-czt-planar-detector-array.html
