## Overview
Surface passivation reduces leakage current in CZT strip detectors by (1) neutralizing or removing surface states that trap or emit carriers, (2) preventing adsorption of ionic/aqueous contaminants, and (3) providing a stable dielectric/interface that shapes surface fields. Effective methods combine appropriate cleaning/etching, choice of dielectric/passivant, interface engineering, and environmental sealing. Below are the technically validated approaches and practical considerations.
## Pre-passivation surface preparation
- Solvent and DI-water cleaning: remove organics and particulates using filtered solvents (acetone → isopropyl alcohol) followed by deionized water rinses; handle in cleanroom conditions.
- Light chemical etch / surface conditioning: brief controlled etches (e.g., dilute bromine–methanol or bromine–ethanol) remove a damaged polishing layer and reduce shallow defect density; strictly time-controlled to avoid stoichiometry change.
- Neutralization and thorough rinsing: immediately neutralize and rinse etchants to remove ionic residues that would increase surface conductivity.
- Drying and contamination control: dry with filtered N2 and minimize exposure to ambient humidity/contaminants before passivation deposition.
## Inorganic dielectric passivants
- ALD Al2O3 (aluminum oxide):
- Advantages: highly conformal, excellent interface quality, strong chemical inertness, and controllable fixed charge (often negative) that can repel majority carriers from the surface.
- Suitable for: narrow inter-strip gaps and trench conformality; deposited at relatively low temperatures (compatible with CZT).
- Considerations: ALD process parameters must be tuned to minimize interfacial defect states; thickness typically a few to tens of nm depending on needs.
- PECVD SiO2 / Si3N4 (silicon dioxide / silicon nitride):
- Advantages: established dielectric properties, good barrier to moisture, and mechanical robustness for passivation and planarization layers.
- Suitable for: planar passivation and where thicker coatings are acceptable; Si3N4 offers higher dielectric strength and mechanical protection.
- Considerations: PECVD deposition introduces film stress and may require low-temperature recipes; interface conditioning beneficial before deposition.
- Sputtered oxides / amorphous oxides (e.g., ZnO variants):
- Advantages: alternative materials with different band alignments; sometimes used for specific interface behavior.
- Considerations: process control and adhesion must be validated to avoid micro-cracking or pinholes.
## Polymeric and conformal organic passivants
- Parylene (poly-para-xylylene)
- Advantages: room-temperature CVD deposition yields pinhole-free, conformal, low-stress coatings; excellent moisture barrier; useful for covering complex geometries and encapsulating interconnects.
- Considerations: Parylene is an insulator that can trap charges over long times and may outgas if not properly processed; adhesion promoters may be required.
- Polyimides and spin-on polymers
- Advantages: planarization capability, relatively straightforward deposition, and compatibility with photolithographic patterning.
- Considerations: polymeric layers are typically less robust under radiation and may absorb moisture unless overcoated; thermal stability must match processing constraints.
## Hybrid dielectric stacks and interface engineering
- Thin interfacial “seed” oxide + high-quality passivant: deposit a thin (few nm) controlled oxide or ALD layer to improve adhesion and limit interface traps, then overcoat with a thicker dielectric (Al2O3, SiO2/Si3N4 or polymer). This reduces interface-state density and mechanical delamination risk.
- Charge-engineered stacks: choose/passivate layers (e.g., Al2O3 with negative fixed charge) to produce an electric field at the surface that repels majority carriers, reducing surface leakage.
- Multilayer dielectric (Al2O3 + SiO2 or Si3N4): combine the chemical/interface benefits of Al2O3 with the mechanical/moisture-barrier properties of SiO2/Si3N4 or parylene.
## Edge termination and localized surface treatments
- Beveling/chamfering and passivated bevels: mechanically bevel edges to reduce field concentration and coat bevels with dielectric to prevent edge leakage.
- Guard rings and field plates over passivation: patterned guard rings (metal) deposited over or adjacent to passivation, biased to capture leakage currents and flatten surface potential; field plates over dielectric can suppress high-field regions at strip edges.
- Grooves/trenches + passivation: shallow isolation trenches between strips (etched and cleaned) filled or coated with dielectric to increase lateral resistance and lengthen leakage paths.
## Hydrophobic surface treatments and moisture control
- Hydrophobic silane treatments: apply compatible silane-based hydrophobic monolayers on top of an inorganic dielectric (when adhesion and compatibility permit) to inhibit adsorption of water and ions that increase surface conductivity.
- Hermetic packaging / conformal sealing: integrating passivation with hermetic module-level sealing (epoxy with low-moisture permeation, metal/glass sealing, or desiccated enclosures) prevents humidity-driven leakage increases over time.
## Contact/interface metallurgy considerations
- Avoid direct metal-semiconductor exposure in inter-strip regions: restrict metallization to strip electrodes and guard rings; ensure passivation covers exposed CZT surfaces to prevent metal-induced leakage.
- Barrier/adhesion layers: use thin adhesion or barrier layers under contact metallization to prevent diffusion or reaction that creates surface states at metal-semiconductor interfaces.
- Annealing restraint: avoid high-temperature anneals that can alter CZT stoichiometry or create Te precipitation; passivation processes must be compatible with low thermal budgets.
## Process control, inspection, and defect mitigation
- Pinholes and defect inspection: use optical, electrical (leakage mapping), and microscopy inspection to detect pinholes or delamination; localized defects are major leakage sources.
- Electrical characterization: map inter-strip leakage vs. bias and humidity after each process step; iterate process to minimize worst-case leakage.
- Compatibility testing: validate passivation radiation hardness, thermal cycling, and long-term stability specifically for intended operating environment (e.g., space, lab, or clinical).
## Examples of practical recipes and trade-offs
- ALD Al2O3 (~10–30 nm) followed by PECVD SiO2 (~100–500 nm) or parylene overcoat: combines excellent interface passivation, negative fixed charge, mechanical protection, and moisture barrier—widely adopted for good leakage performance.
- Single ALD Al2O3: minimal thickness and excellent conformality for narrow gaps; best when thickness and dielectric constant trade-offs for inter-strip capacitance are considered.
- Parylene conformal coat alone: fast deployment for humidity protection but less ideal alone for interface-state reduction unless preceded by an inorganic seed layer.
## Limitations and failure modes
- Charge trapping in passivation: some dielectrics can accumulate fixed charge over time leading to bias shifts; selection and process control mitigate this.
- Radiation-induced degradation: polymers and some dielectrics may degrade under ionizing radiation, increasing leakage—must be qualified for astrophysics or high-dose applications.
- Thermal/mechanical stress: CTE mismatch can induce cracks or delamination; low-stress deposition methods and compliant underlayers reduce risk.
## Summary
Effective reduction of leakage current in CZT strip detectors relies on meticulous surface preparation followed by a passivation strategy tailored to the geometry and operating environment. ALD Al2O3 (often as an interfacial layer) plus a robust overcoat (PECVD SiO2/Si3N4 or parylene) is a widely effective approach: it combines excellent interface passivation, charge engineering to repel carriers, conformality for narrow gaps, and mechanical/moisture protection. Complement with edge termination, guard rings, hermetic packaging, and rigorous process/instrumentation controls to achieve low, stable inter-strip leakage.
CdZnTe Association (CdZnTe.com)
https://www.cdznte.com/blog/what-surface-passivation-methods-are-effective-for-reducing-leakage-current-in-czt-strip-detectors.html
